include "stm32f10x.h"

include <stdio.h>

//定义ADC1采样通道数据寄存器地址（共16个通道）

define ADC1_DR_Address ((u32)0x4001244C) //ADC1数据寄存器地址

//定义GPIO端口地址
#define GPIOA_BASE (u32)0x40010800 //GPIOA的起始地址

//定义显示端口引脚宏定义
#define LED_PAout(n) GPIOA->ODR^=(1<<(n)) //LED显示端口引脚设置函数

/ADC初始化函数**/
void ADC1_Init(void) //ADC初始化函数，用于初始化STM32内部的ADC功能。
{

RCC->APB2ENR|=1<<2; //使能PORTA时钟 (bit 2 APB2ENR: IO port A clock enable )

RCC->APB2ENR|=1<<9; //使能ADC时钟 (bit 9 APB2ENR: ADC 1 interface clock enable )

GPIOA->CRH&=0XFFFFFFF0; //PA5 清除之前设置 (bit 0~3 CRH: PA5 clear bit )

GPIOA->CRH|=12; //PA5 设置为AIN (bit 0~3 CRH: PA5 mode is input analog mode )

RCC->CFGR&=~(3<<14); //复位SW[1:0] (bit 14~15 CFGR: SW clear bit )

RCC->CFGR|=2<<14; //PLL作为系统时钟 (bit 14~15 CFGR: SW set 02, select PLL as system clock source )

ADC1->CR1&=~(7<<24); //复位JEXTEN[2:0] (bit 24~26 CR1 : JEXTEN clear bit )

ADC1->CR2&=~(3<<17); //复位EXTSEL[2:0] (bit 17~19 CR2 : EXTSEL clear bit )

ADC1->CR2|=7<<17 ; //TIM4 TRGO (bit 17~19 CR2 : EXTSEL set 111, select TIM4 TRGO event as conversion trigger for regular channels)

ADC ->SQR1 &=~(31 << 20 );//复位SQ16[4：0] （Bit20-24 SQR13 项目序列 加上此行代码清零，以便后面赋值 ） / Clear the old SQ16 bits / / Clear the old SQ16 bits / / Set channel 16 as the last conversion in regular sequence / / Set channel 16 as the last conversion in regular sequence / / Select Channel 16 for conversion / / Select Channel 16 for conversion / ADCs ->SQR3 | = 15 << 0 ;//通道16 （Bit 0-4 SQR3 项目序列 加上此行代码将通道号写入末尾 ） / 将通道16作为常规序列中的最后一次转换 / / 将通道16作为常规序列中的最后一次转换 / / 选择通道16进行转换 / / 选择通道16进行转换 / ADCs ->JSQRR | = 15 << 20 ;//injected channel 16 （Bit20-24 JSQRR 注射序列加上此行代码将注射信道写入末尾） / Set injected sequency length to 1 , only convert once per injected group/ / Set injected sequency length to 1 , only convert once per injected group/ / Select Channel 16 for injected group sequency / / Select Channel 16 for injected group sequency / ADCs ->SMPR 2 | = 7 << 12 ;//采样时间239.5周期 （Bit12-14 SMPR 2 采样时间 加上此行代码即可修正采样周期） ADCs ->SMPR 2 | = 7 << 24 ;/ Same sample time configuration for all channels/ ADCs ->SMPR 2 | = 7 << 24 ;/ Same sample time configuration for all channels/ ADCs ->SMPR 1 | = 7 << 6 ;/ Same sample time configuration for all channels/ ADCs ->SMPR 1 | = 7 << 18 ;/ Same sample time configuration for all channels/ ADCs ->SMPR 0 | = 7 << 0 ;/ Same sample time configuration for all channels/ Adcs - > SMPRO | -7 < 12;/ same sample time Configuration For All Channels / Adcs - > SMPRO | -7 < 24;/ same Sample Time Configuration For All Channels / Adcs - > SMPRO | -7 < 36;/ same Sample Time Configuration For All Channels