module i3c_slave (
    // inputs 
    input wire clk, 
    input wire reset, 

    // outputs  
    output wire sda_out, 

    // bidirectional signals  
    inout wire sda_in  
);

    // internal variables 
    reg [7:0] data; // 8-bit data to be transferred

    always @ (posedge clk or posedge reset) begin 

        if (reset) begin // reset logic  
            data <= 8'h00; // set data to 0x00 when reset is activated.  

        end else begin // normal operation logic  

            case (sda_in) begin     // slave output logic on SDA line     

                1'b1: sda_out <= ~data[0];     // send out the LSB of the data on SDA line when SCL is high.      

                default: sda_out <= 1'bz;       // keep SDA line in high impedance state otherwise.     

            endcase        

            if (~sda_in && scl) begin           // slave receive logic on SDA line        
                data <= {data[6:0], ~sda_in};    // shift in 1 bit of data from the master.     
            end    

        end                                                                                                                  
    end                
                                                        
                                                                                                                          
    assign scl = ~scl;